--
-- VHDL Architecture Fietscomputer_lib.gen_divider.combi
--
-- Created:
--          by - jcmooije.UNKNOWN (dtp7985)
--          at - 16:56:30  7-07-2010
--
-- using Mentor Graphics HDL Designer(TM) 2007.1 (Build 19)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;

ENTITY fc_gen_divider IS
  GENERIC( 
  na : NATURAL := 64;
  nb : NATURAL := 64;
  nq : NATURAL := 64
  );
  PORT( 
  a     : IN     STD_LOGIC_VECTOR(63 DOWNTO 0);
  b     : IN     STD_LOGIC_VECTOR(63 DOWNTO 0);
  q     : OUT    STD_LOGIC_VECTOR(63 DOWNTO 0);
  start : IN     STD_LOGIC;
  clk   : IN     STD_LOGIC;
  rst   : IN     STD_LOGIC;
  ready : OUT    STD_LOGIC
  );
  
  -- Declarations
  
END fc_gen_divider ;

--
ARCHITECTURE combi OF fc_gen_divider IS



SIGNAL areg : STD_LOGIC_VECTOR(na-1 DOWNTO 0);
SIGNAL breg : STD_LOGIC_VECTOR(nb-1 DOWNTO 0);
SIGNAL qreg : STD_LOGIC_VECTOR(nq-1 DOWNTO 0);
SIGNAL cntr : NATURAL RANGE 0 TO 1;


BEGIN
  
  
  PROCESS(rst, clk)
    VARIABLE aint : NATURAL;
    VARIABLE bint : NATURAL;
    VARIABLE qint : NATURAL;
    
    BEGIN
      IF rst = '1' THEN
        areg <= (OTHERS => '0');
        breg <= (OTHERS => '0');
        qreg <= (OTHERS => '0');
        cntr <=  0;
        ready <= '0';
      ELSIF RISING_EDGE(clk) THEN
        
        IF start = '1' THEN
          areg <= a(na -1 DOWNTO 0);
          breg <= b(nb -1 DOWNTO 0);
          cntr <= 1;
        ELSIF cntr > 0 THEN
          aint := CONV_INTEGER(areg);
          bint := CONV_INTEGER(breg);
          IF bint = 0 THEN
            qint := aint;
          ELSE          
            qint := aint / bint;
          END IF;
                   
          qreg <= CONV_STD_LOGIC_VECTOR(qint,nq);
          cntr <= cntr - 1;
        END IF;  
        
        IF cntr = 1 THEN
          ready <= '1';
        ELSE
          ready <= '0';
        END IF;
        
      END IF;
    END PROCESS;
    
    
    
    
    q(nq-1 DOWNTO  0) <= qreg;
    q(  63 DOWNTO nq) <= (OTHERS => '0');
    
    
  END ARCHITECTURE combi;
  
  
  